Low cost anti-fuse structure and method to make same

ABSTRACT

An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.13/552,293, filed Jul. 18, 2012, the entire content and disclosure ofwhich is incorporated herein by reference.

BACKGROUND

The present disclosure relates to a semiconductor structure and a methodof forming the same. More particularly, the present disclosure relatesto a semiconductor structure including an anti-fuse structure locatedwithin an interconnect dielectric material and a method of forming thesame.

Anti-fuse structures have been used in the semiconductor industry formemory related applications such as, for example, field programmablegate arrays and programmable read-only memories. Most existing anti-fusestructures have a layer of anti-fuse material sandwiched in between twodisconnected conductive materials. In such structures, the anti-fusestructure/circuit initially has a very high resistance, but afterprogramming by electrical or optical means, the high resistancestructure/circuit is converted to a lower resistance state.

Prior art processes for integrating anti-fuse structures within aninterconnect structure require many extra masking and etching stepswhich increase the overall cost of fabricating an integrated circuit.Therefore, a cost effective means for integrating an anti-fuse structurewithin an interconnect structure is needed which does not require anyextra masking and etching steps.

SUMMARY

The present disclosure provides an anti-fuse structure in which ananti-fuse material liner is embedded within one of the openings providedwithin an interconnect dielectric material. The anti-fuse material lineris located between a first conductive metal and a second conductivemetal which are also present within the opening. A diffusion barrierliner separates the first conductive metal from any portion of theinterconnect dielectric material. The anti-fuse structure is laterallyadjacent an interconnect structure that is formed within the sameinterconnect dielectric material as the anti-fuse structure.

In one aspect of the present disclosure, a semiconductor structure isprovided. The semiconductor structure includes an interconnectdielectric material having at least one opening located therein. Thesemiconductor structure further includes an anti-fuse structure locatedwithin the least one opening. The anti-fuse structure includes adiffusion barrier liner located within the at least one opening and indirect contact with at least sidewall surfaces of the interconnectdielectric material, a first conductive metal plug located within the atleast one opening and located on an exposed surface of the diffusionbarrier liner. The first conductive metal plug includes verticalsidewall portions that extend upward from an uppermost surface of thefirst conductive metal plug. The anti-fuse structure further includes ananti-fuse material liner located on an exposed surface of the firstconductive metal plug and an exposed surface of the vertical sidewallportions, and a second conductive metal plug located on an exposedsurface of the anti-fuse material liner. In accordance with the presentdisclosure, each of the diffusion barrier liner, the vertical sidewallportions, the anti-fuse material liner and the second conductive metalplug have an uppermost surface that is co-planar with an uppermostsurface of the interconnect dielectric material.

In another aspect of the present disclosure, a method of forming asemiconductor structure is provided. The method of the presentdisclosure includes forming at least one opening within an interconnectdielectric material; and forming an anti-fuse structure within the leastone opening. The forming of the anti-fuse structure includes forming acontiguous layer of a diffusion barrier material on an exposed uppermostsurface of the interconnect dielectric material and at least within theat least one opening; forming a contiguous layer of a first conductivemetal on an exposed surface of the contiguous layer of the diffusionbarrier material; performing a reflow anneal which causes portions ofthe contiguous layer of the first conductive metal to flow into the atleast one opening forming a first conductive metal plug within the atleast one opening, wherein a remaining portion of the contiguous layerof the first conductive metal which is present inside and outside the atleast one opening remains in contact with the first conductive metalplug; forming a contiguous layer of an anti-fuse material on exposedsurfaces of the first conductive metal plug and the remaining portion ofthe contiguous layer of the first conductive metal; forming a contiguouslayer of a second conductive metal on an exposed surface of thecontiguous layer of the anti-fuse material; and removing a portion ofthe contiguous layer of the second conductive metal, a portion of thecontiguous layer of the anti-fuse material, remaining portions of thecontiguous layer of the first conductive metal, and a portion of thecontiguous layer of the diffusion barrier material that are locatedoutside of the at least one opening.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial representation (through a cross sectional view)illustrating an interconnect dielectric material including at least oneinterconnect area and at least one anti-fuse area.

FIG. 2 is a pictorial representation (though a cross sectional view)illustrating the structure of FIG. 1 after forming at least one firstopening within the interconnect dielectric material in the at least oneinterconnect area and at least one second opening within theinterconnect dielectric material in the at least one anti-fuse area,wherein the at least one first opening and the at least one secondopening are formed simultaneously and are laterally adjacent to eachother.

FIG. 3 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 2 after forming at least a contiguouslayer of a diffusion barrier material within the at least one firstopening and the at least one second opening.

FIG. 4 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 3 after formation of a contiguouslayer of a first conductive metal atop the contiguous layer of diffusionbarrier material.

FIG. 5 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 4 after performing a reflow annealwhich partially fills the at least one first and second openings with afirst conductive metal plug.

FIG. 6 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 5 after forming a mask within the atleast one interconnect area of the structure.

FIG. 7 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 6 after forming a contiguous layer ofan anti-fuse material in the at least one anti-fuse area of thestructure, wherein a portion of the contiguous layer of anti-fusematerial is present within the at least one second opening.

FIG. 8 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 7 after removing the mask within theat least one interconnect area of the structure and forming a contiguouslayer of a second conductive metal within both the at least oneinterconnect area and the at least one anti-fuse area.

FIG. 9 is a pictorial representation (through a cross sectional view)illustrating the structure of FIG. 8 after performing a planarizationprocess.

DETAILED DESCRIPTION

The present disclosure, which provides a semiconductor structureincluding an anti-fuse structure located within an interconnectdielectric material and a method of forming the same, will now bedescribed in greater detail by referring to the following discussion anddrawings that accompany the present application. It is noted that thedrawings of the present application are provided for illustrativepurposes and, as such, they are not drawn to scale. In the drawings andthe description that follows, like materials are referred to by likereference numerals. For purposes of the description hereinafter, theterms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”,“top”, “bottom”, and derivatives thereof shall relate to the components,layers and/or materials as oriented in the drawing figures whichaccompany the present application.

In the following description, numerous specific details are set forth,such as particular structures, components, materials, dimensions,processing steps and techniques, in order to provide a thoroughunderstanding of the present invention. However, it will be appreciatedby one of ordinary skill in the art that the present disclosure may bepracticed with viable alternative process options without these specificdetails. In other instances, well-known structures or processing stepshave not been described in detail in order to avoid obscuring thevarious embodiments of the present disclosure.

Specifically, FIG. 1 illustrates an initial structure that includes aninterconnect dielectric material 12 which includes at least oneinterconnect area 14 and at least one anti-fuse area 16. The term“interconnect area” denotes a portion of the interconnect dielectricmaterial in which an interconnect structure is present. The interconnectstructure includes conductive wiring in the form of vias and/or linesembedded within the interconnect dielectric material. The conductivewiring connects semiconductor devices that are located beneath theinterconnect dielectric material to other components within anintegrated circuit. The term “anti-fuse area” denotes a portion of theinterconnect dielectric material in which an anti-fuse structure ispresent. The anti-fuse structure includes an anti-fuse materialpositioned between a first conductive material and a second conductivematerial. The anti-fuse structure initially has a very high resistance,but after programming by electrical or optical means, the highresistance material is converted to a lower resistance state.

Interconnect dielectric material 12 may be located upon a substrate (notshown in the drawings of the present application). The substrate, whichis not shown, may comprise a semiconducting material, an insulatingmaterial, a conductive material or any combination thereof. When thesubstrate is comprised of a semiconducting material, any semiconductingmaterial such as Si, SiGe, SiGeC, SiC, Ge alloys, GaAs, InAs, InP andother III/V or II/VI compound semiconductors may be used. In addition tothese listed types of semiconducting materials, the present disclosurealso contemplates cases in which the semiconductor substrate is alayered semiconductor such as, for example, Si/SiGe, Si/SiC,silicon-on-insulators (SOIs) or silicon germanium-on-insulators (SGOIs).When the substrate comprises a semiconducting material, one or moresemiconductor devices such as, for example, complementary metal oxidesemiconductor (CMOS) devices can be fabricated thereon.

When the substrate is an insulating material, the insulating materialcan be an organic insulator, an inorganic insulator or a combinationthereof including multilayers. When the substrate is a conductivematerial, the substrate may include, for example, polySi, a conductivemetal, alloys of at least two conductive metals, a metal silicide, ametal nitride or combinations thereof including multilayers. When thesubstrate comprises a combination of an insulating material and aconductive material, the substrate may represent a first interconnectlevel of a multilayered interconnect structure.

The interconnect dielectric material 12 can include any interlevel orintralevel dielectric including inorganic dielectrics or organicdielectrics. In one embodiment, the interconnect dielectric material 12may be non-porous. In another embodiment, the interconnect dielectricmaterial 12 may be porous. Porous dielectrics are advantageous sincesuch dielectric materials have lower dielectric constants than anequivalent non-porous dielectric material. Some examples of suitabledielectrics that can be used as the interconnect dielectric material 12include, but are not limited to, SiO₂, silsesquioxanes, C doped oxides(i.e., organosilicates) that include atoms of Si, C, O and H,thermosetting polyarylene ethers, or multilayers thereof. When amultilayered interconnect dielectric material structure is employed, thevarious dielectric material layers are typically in direct contact witheach other. The term “polyarylene” is used in this application to denotearyl moieties or inertly substituted aryl moieties which are linkedtogether by bonds, fused rings, or inert linking groups such as, forexample, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like.

In one embodiment, the interconnect dielectric material 12 has adielectric constant that is about 4.0 or less. In another embodiment,the interconnect dielectric material 12 has a dielectric constant ofabout 2.8 or less. All dielectric constants mentioned herein arerelative to a vacuum, unless otherwise noted. The interconnectdielectric material 12 that is employed in the present disclosuregenerally has a lower parasitic crosstalk as compared with dielectricmaterials that have a dielectric constant of greater than 4.0. Thethickness of the interconnect dielectric material 12 may vary dependingupon the dielectric material used as well as the exact number ofdielectrics layers within the interconnect dielectric material 12.Typically, and for normal interconnect structures, the interconnectdielectric material 12 has a thickness from 50 nm to 1000 nm.

Referring now to FIG. 2, there is shown the initial structure of FIG. 1after forming at least one first opening 18L within the interconnectdielectric material 12 in the interconnect area 14 and at least onesecond opening 18R within the interconnect dielectric material 12 in theanti-fuse area 16. The at least one first opening 18L and the at leastone second opening 18R are formed simultaneously and represent acomplementary pair of openings that are laterally adjacent to eachother, but located within different areas of the interconnect dielectricmaterial 12. As shown, the at least one first opening 18L has anuppermost portion that is coincident to an uppermost portion of the atleast one second opening 18R. Also, the at least one first opening 18Lhas a bottommost portion that is coincident to a bottommost portion ofthe at least one second opening 18R.

Although a single first opening 18L and a single second opening 18R areshown in the drawings, a plurality of such openings can be formed. Whena plurality of first and second openings 18L, 18R are formed, eachcorresponding first opening 18L and second opening 18R can have a sameor a different depth. In some embodiments (not shown), the bottommostsurface of the first and second openings 18L, 18R does not extendentirely through the interconnect dielectric material 12. In otherembodiments (and as shown in FIG. 2), the first and second openings 18L,18R extend entirely through the interconnect dielectric material 12.Also, and when a plurality of first and second openings 18L, 18R areformed, each first and second opening 18L, 18R can be of a same type orof a different type.

The first and second openings 18L, 18R can be formed into theinterconnect dielectric material 12 utilizing lithography and etching.The lithographic process can include forming a photoresist (not shown)atop the interconnect dielectric material 12, exposing the photoresistto a desired pattern of radiation and developing the exposed photoresistutilizing a conventional resist developer. The pattern is thentransferred into the underlying interconnect dielectric material 12 byetching. The etching can include a dry etching process (such as, forexample, reactive ion etching, ion beam etching, plasma etching or laserablation), and/or a wet chemical etching process. Typically, reactiveion etching is used in providing the first and second openings 18L, 18R.After patterning the underlying interconnect dielectric material 12, thepatterned photoresist can be removed utilizing a conventional strippingprocess such as, for example, ashing.

In one embodiment and prior to patterning the interconnect dielectricmaterial 12, a hardmask (not shown) can be formed directly on anuppermost surface of the interconnect dielectric material 12. Whenemployed, the hard mask can include an oxide, a nitride, an oxynitrideor any multilayered combination thereof. In one embodiment, the hardmask is an oxide such as silicon dioxide, while in another embodimentthe hard mask is a nitride such as silicon nitride. The hard mask can beformed utilizing a conventional deposition process including, forexample, chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), chemical solution deposition, evaporation, andphysical vapor deposition (PVD). Alternatively, the hard mask can beformed by one of thermal oxidation, and thermal nitridation.

When employed, the thickness of the hard mask is from 5 nm to 100 nm.Other thicknesses that are greater than or lesser than the thicknessrange mentioned above can also be employed for the hard mask. When ahard mask is present, a first etch is performed to transfer the patternprovided in the photoresist to the hard mask, the patterned photoresistis then removed by an ashing step, and thereafter, a second etch isperformed to transfer the pattern from the patterned hard mask into theunderlying interconnect dielectric material 12. In embodiments in whicha hard mask is present, the hard mask can be removed from atop theinterconnect dielectric material 12 after the first and second openings18L, 18R are formed therein.

The first opening 18L and the second opening 18R that are formed intothe interconnect dielectric material 12 can be a via opening, a lineopening, and/or combined via/line opening. In FIG. 2, and by way of anexample, a line opening is shown for the first opening 18L and thesecond opening 18R. When combined via/line openings are formed, theindividual via opening and line opening of a combined via and lineopening are in communication with each other. When a combined via andline opening is formed, a second iteration of lithography and etchingcan be used in forming the same. A via opening can be distinguished froma line opening, in that a via opening has a width that is less than awidth of the line opening.

The width of each first opening 18L and second opening 18R may varydepending on the type of opening formed and should be sufficiently smallso as to allow partial filling of the opening by a metal reflow process.For a via opening, the width of the via opening can be from 10 nm to 200nm. For line openings, the width of the line opening can be from 20 nmto 2000 nm.

Referring now to FIG. 3, there is illustrated the structure of FIG. 2after forming at least a contiguous layer of a diffusion barriermaterial 20 on all exposed surfaces of the structure including withineach first opening 18L and second opening 18R and along the uppermostsurface of interconnect dielectric material 12. The terms “contiguously”or “contiguous” denotes that a particular layer such as the diffusionbarrier material does not include any breaks therein. The contiguouslayer of diffusion barrier material 20 within the first and secondopenings 18L, 18R does not completely fill each opening, but rather thecontiguous layer of diffusion barrier material 20 is present along thesidewalls and bottommost surface of each first and second openings 18L,18R. Within each first and second opening 18L, 18R, the contiguous layerof diffusion barrier material 20 is present at least on sidewallsurfaces of the interconnect dielectric material 12.

The contiguous layer of diffusion barrier material 20 includes Co, Ir,Pt, Pd, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, WN or any othermaterial that can serve as a barrier to prevent a conductive materialfrom diffusing there through. The thickness of the contiguous layer ofdiffusion barrier material 20 may vary depending on the depositionprocess used as well as the material employed. In one embodiment, thecontiguous layer of diffusion barrier material 20 has a thickness from 2nm to 50 nm. In another embodiment, the contiguous layer of diffusionbarrier material 20 has a thickness from 5 nm to 20 nm.

The contiguous layer of diffusion barrier material 20 can be formed by adeposition process including, for example, chemical vapor deposition(CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layerdeposition (ALD), physical vapor deposition (PVD), sputtering, chemicalsolution deposition and plating.

In some embodiments (now shown), an optional plating seed layer can beformed on an exposed uppermost surface of the contiguous layer ofdiffusion barrier material 20. The optional plating seed layer isemployed to selectively promote subsequent electroplating of apre-selected conductive metal or metal alloy. The optional plating seedlayer may comprise Cu, a Cu alloy, Ir, an Ir alloy, Ru, a Ru alloy(e.g., TaRu alloy) or any other suitable noble metal or noble metalalloy having a low metal-plating overpotential. Typically, Cu or a Cualloy plating seed layer is employed, when a Cu metal is to besubsequently formed within the at least one opening. The thickness ofthe optional seed layer may vary depending on the material of theoptional plating seed layer as well as the technique used in forming thesame. Typically, the optional plating seed layer has a thickness from 2nm to 80 nm. The optional plating seed layer can be formed by aconventional deposition process including, for example, CVD, PECVD, ALD,and PVD.

Referring now to FIG. 4, there is illustrated the structure of FIG. 3after forming a contiguous layer of a first conductive metal 22 atop thecontiguous layer of diffusion barrier material 20. As such, thecontiguous layer of first conductive metal 22 will be present inside andoutside of each of the first and second openings 18L, 18R within theinterconnect area 14 and the anti-fuse area 16 of the structure. Thecontiguous layer of first conductive metal 22 within the first andsecond openings 18L, 18R does not completely fill each opening, butrather the contiguous layer of first conductive metal 22 is presentalong the sidewalls and bottommost surface of each first and secondopenings 18L, 18R.

The contiguous layer of first conductive metal 22 can include aconductive metal, an alloy comprising at least two conductive metals, aconductive metal silicide or combinations thereof. In one embodiment,the contiguous layer of first conductive metal 22 is a conductive metalsuch as, for example, Cu, W or Al. In another embodiment, the contiguouslayer of first conductive metal 22 is comprised of a Cu alloy (such asAuCu or AlCu or CuMn).

The contiguous layer of conductive metal 22 can be formed by adeposition process including, for example, chemical vapor deposition(CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layerdeposition (ALD), physical vapor deposition (PVD), sputtering, chemicalsolution deposition and plating.

The contiguous layer of first conductive metal 22 that is formed at thispoint of the present disclosure must be thick enough such that during asubsequent reflow anneal each of the first and second openings 18L, 18Ris partially filled with a first conductive metal plug. It is noted thatthe first conductive metal plug comprises the conductive material of thecontiguous layer of first conductive metal 22 which was subjected to thereflow anneal. In one embodiment, the contiguous layer of firstconductive metal 22 has a thickness from 2 nm to 80 nm. In anotherembodiment, the contiguous layer of first conductive metal 22 has athickness from 4 nm to 50 nm.

Referring now to FIG. 5, there is illustrated the structure of FIG. 4after performing a reflow anneal. During the reflow anneal, a portion ofthe contiguous layer of first conductive metal 22 that is locatedoutside the first and second openings 18L, 18R flows into each openingfilling at least a portion of the first and second openings 18L, 18Rwith first conductive metal plug 25. A cavity 15 remains in each of thefirst and second openings 18L, 18R which does not extend the entireheight of each first and second opening 18L, 18R. As shown in FIG. 5, aremaining portion 21 of the contiguous layer of first conductive metal22 is located inside and outside of the first and second openings 18L,18R. As also shown in FIG. 5, the remaining portion 21 of the contiguouslayer of first conductive metal 22 is in direct physical contact withthe first conductive metal plug 25 that is formed within each of thefirst and second openings 18L, 18R. As mentioned above, the firstconductive metal plug 25 comprises the conductive material of thecontiguous layer of first conductive metal 22 which was subjected to thereflow anneal. As shown in the drawings, no interface separates theremaining portion 21 of the contiguous layer of first conductive metal22 from that of the first conductive metal plug 25 since the remainingportion 21 of the contiguous layer of first conductive metal 22 and thefirst conductive metal plug 25 are both composed of the same materialand no other material is formed between elements 21 and 25 in thepresent disclosure. As such, the first conductive metal plug 25 and theremaining portion 21 of the contiguous layer of first conductive metal22 are of unitary construction, i.e., elements 21 and 25 are one piece.In the drawings, a dashed line is used to emphasize the location ofelement 21 in relationship to element 25.

In one embodiment, the reflow anneal can be performed at a temperaturefrom 150° C. to 400° C. for a time period from 5 minutes to 500 minutes.In another embodiment, the reflow anneal can be performed at atemperature from 200° C. to 300° C. for a time period from 20 minutes to100 minutes. In one embodiment, the reflow anneal can be performed in ahydrogen-containing ambient. By “hydrogen-containing ambient” it ismeant an environment that includes hydrogen. In one embodiment, thehydrogen-containing ambient may include a mixture of hydrogen andnitrogen. In another embodiment, the reflow anneal can be formed in anitrogen-containing ambient which includes at least nitrogen. In oneembodiment, the nitrogen-containing ambient may include nitrogen.Without wishing to be bound by any theory, it is believed that theduring the reflow anneal, the surface energy of the structure is reducedin such a manner that a majority, but not all, of the contiguous layerof first conductive metal 22 that is located outside the first andsecond openings 18L, 18R, i.e., on the field region of the structure,flows into the small features of the first and second openings 18L, 18R,and partially fills the first and second openings 18L, 18R with a firstconductive metal plug 25.

Referring now to FIG. 6, there is illustrated the structure of FIG. 5after forming a mask 24 within the at least one interconnect area 14 ofthe structure. As shown, the mask 24 covers the entirety of the at leastone interconnect area 14 while leaving the at least one anti-fuse area16 exposed. The mask 24 has a bottommost surface that contacts the firstconductive metal plug 25 within the at least one interconnect area 14 ofthe structure.

In one embodiment of the present disclosure, the mask 24 may comprise ahard mask material such as for example, silicon dioxide, siliconnitride, silicon oxynitride or any multilayered combination thereof. Inanother embodiment, the mask 24 may comprise any photoresist material.

The mask 24 can be formed by first forming a blanket layer of maskmaterial within both the at least one interconnect area 14 and the atleast one anti-fuse area 16. The blanket layer of mask material can thenbe patterned such that the mask material is removed from within the atleast one anti-fuse area 16, while leaving mask material within the atleast one interconnect area 14. The blanket layer of mask material canbe formed by a deposition process such as, for example, chemical vapordeposition (CVD), plasma enhanced chemical vapor deposition (PECVD),chemical solution deposition, evaporation, physical vapor deposition(PVD) and spin-on coating. The patterning of the blanket layer of maskmaterial may comprise lithography and etching. In embodiments in which ahard mask material is employed as mask 24, a separate photoresist isemployed atop the blanket layer of hard mask material prior tolithography. Lithography includes exposing a photoresist material to adesired pattern of radiation and then developing the exposed photoresistmaterial. In some embodiments, the pattern can be transferred into theblanket layer of mask material utilizing an etching process such as adry etching or wet chemical etching process. The pattern transferutilizing one of the etching process is typically required when the maskmaterial is other than a photoresist material. When the mask material isa photoresist material, the lithography step can be used to directlypattern the blanket layer of photoresist material into mask 24.

Referring now to FIG. 7, there is illustrated the structure of FIG. 6after forming a contiguous layer of an anti-fuse material 26 within theat least one anti-fuse area 16 of the structure. No anti-fuse material26 forms on the active components within the at least one interconnectarea 14 because of the presence of the mask 24. The contiguous layer ofanti-fuse material 26 is formed on an exposed surface of the firstconductive metal plug 25 and all exposed surfaces of the remainingportion 21 of the contiguous layer of first conductive metal 22.

The contiguous layer of anti-fuse material 26 includes an insulator orsemiconductor material, which makes the original anti-fusestructure/circuit have an initial high electrical resistance. This highresistance structure/circuit can be programmed into a lower resistanceby application of certain process such as, for example, an electricalpulse or a laser. By “high” and “low” resistances, it is meant anelectrical resistance reduction of 50% or greater. Examples of anti-fusematerials that can be used as the contiguous layer of anti-fuse material26 include, but are not limited to, silicon dioxide, hafnium dioxide,nickel oxide, tantalum oxide, copper oxide, amorphous silicon carbide,amorphous silicon, diamond like carbon and any combination thereofincluding multilayers.

The contiguous layer of anti-fuse material 26 can be formed utilizing adeposition process including for example, chemical vapor deposition(CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layerdeposition (ALD), physical vapor deposition (PVD), sputtering, chemicalsolution deposition and plating.

The thickness of the contiguous layer of anti-fuse material 26 may varydepending on type of anti-fuse material employed as well as thetechnique used in forming the same. In one embodiment, the contiguouslayer of anti-fuse material 26 has a thickness from 0.5 nm to 50 nm. Inanother embodiment, the contiguous layer of anti-fuse material 26 has athickness from 1 nm to 20 nm.

Referring now to FIG. 8, there is illustrated the structure of FIG. 7after removing mask 24 and then forming a contiguous layer of a secondconductive metal 28 on all exposed surfaces structure. In the at leastone interconnect area 14, a portion of the contiguous layer of secondconductive metal 28 entirely fills the cavity 15 that remained withinthe first opening 18L, while another portion of the contiguous layer ofsecond conductive metal 28 within the at least one interconnect area 14is located outside the first opening 18L. In the at least one anti-fusearea 16, a portion of the contiguous layer of second conductive metal 28is formed atop the contiguous layer of anti-fuse material 26 filling theremaining portion of the cavity 15 that remained within the secondopening 18R, while another portion of the contiguous layer of secondconductive metal 28 within the at least one interconnect area 16 islocated outside the second opening 18R.

In one embodiment, mask 24 can be removed from the structure utilizingan etching process such as, for example, a chemical wet etch. In anotherembodiment, the mask 24 can be removed from the structure utilizing aresist ashing process. In yet another embodiment, the mask 24 can beremoved by a planarization process such as, for example, chemicalmechanical planarization and/or grinding.

The contiguous layer of second conductive metal 28 comprises one of theconductive materials mentioned above for the contiguous layer of firstconductive metal 22. In one embodiment of the present disclosure, thecontiguous layer of second conductive metal 28 comprises a sameconductive metal as the contiguous layer of first conductive metal 22.In another embodiment of the present disclosure, the contiguous layer ofsecond conductive metal 28 comprises a different conductive metal as thecontiguous layer of first conductive metal 22.

The contiguous layer of second conductive metal 28 may be formedutilizing one of the techniques mentioned above in forming thecontiguous layer of first conductive metal 22. Alternatively, thecontiguous layer of second conductive metal 28 can be formed by otherdeposition techniques such as, for example, PVD, CVD, and ECP(Electrochemical plating). In one embodiment, the contiguous layer ofsecond conductive metal 28 that is formed at this point of the presentdisclosure has a thickness from 2 nm to 100 nm. In another embodiment,the contiguous layer of second conductive metal 28 has a thickness from10 nm to 50 nm.

Referring now to FIG. 9, there is illustrated the structure of FIG. 8after performing a planarization process. The planarization processwhich can be employed in the present disclosure includes, for example,chemical mechanical polishing (CMP) and/or grinding. The planarizationprocess removes all materials that are located on the uppermost surfaceof the interconnect dielectric material 12 and that are present outsideof the first and second openings 18L, 18R. The portion of the contiguouslayer of second conductive metal 28 that remains within the first andsecond openings 18L, 18R after the planarization process is referred toherein as a second conductive metal plug 30. The portion of thecontiguous layer of anti-fuse material 26 that remains within the secondopening 18R is referred to herein as an anti-fuse material liner 26′.The portion of the contiguous diffusion barrier material 20 that remainswithin the first and second openings 18L, 18R is referred to herein asdiffusion barrier liner 20′. Also, present within the first and secondopenings 18L, 18R, after the planarization is performed, is a verticalsidewall portion of the remaining portion 21 of the contiguous layer offirst conductive metal 22 that was left within the openings 18L, 18Rafter the reflow anneal. This vertical sidewall portion of the remainingportion 21 of the contiguous layer of first conductive metal 22 that wasleft within the openings 18L, 18R after the reflow anneal is labeled as21′ in the drawing and can be refer to just as a vertical sidewallportion of the first conductive metal plug 25. Each vertical sidewallportion extends from and uppermost surface of the first conductive metalplug 25. The first conductive metal plug 25 and the vertical sidewallportions 21′ are of unitary construction, i.e., elements 21′ and 25 areone piece. In the drawings, a dashed line is used to emphasize thelocation of element 21′ in relationship to element 22.

The diffusion barrier liner 20′ and the anti-fuse material liner 26′ areU-shaped. By “U-shaped” it is meant that the particular liner materialincludes two vertical portions which upward extend from a horizontalconnecting portion.

Specifically, FIG. 9 illustrates a semiconductor structure in accordancewith an embodiment of the present disclosure. This structure includesinterconnect dielectric material 12 having at least one opening 18Rlocated therein. The structure further includes an anti-fuse structurelocated within the least one opening 18R. The anti-fuse structureincludes diffusion barrier liner 20′ located within the at least oneopening 18R and in direct contact with at least sidewall surfaces of theinterconnect dielectric material 12, first conductive metal plug 25located within the at least one opening 18R and located on an exposedsurface of the diffusion barrier liner 20′. The first conductive metalplug 25 includes vertical sidewall portions (i.e., element 21′) thatextend upward from an uppermost surface of the first conductive metalplug 25. The anti-fuse structure further includes an anti-fuse materialliner 26′ located on an exposed surface of the first conductive metalplug 25 and an exposed surface of the vertical sidewall portions 21′,and a second conductive metal plug 30 is located on an exposed surfaceof the anti-fuse material liner 26′. As shown in FIG. 9, each of thediffusion barrier liner 20′, the vertical sidewall portions 21′, theanti-fuse material liner 26′, and the second conductive metal plug 30have an uppermost surface that is co-planar with an uppermost surface ofthe interconnect dielectric material 12.

An interconnect structure is located within the same interconnectdielectric material 12 and the interconnect structure is laterallyadjacent to the anti-fuse structure. The interconnect structure includesa portion of the interconnect dielectric material which includes atleast one opening 18L. The at least one opening 18L is filled with adiffusion barrier liner 20′ located within the at least one opening 18Land in direct contact with at least sidewall surfaces of theinterconnect dielectric material 12, first conductive metal plug 25located within the at least one opening 18L and located on an exposedsurface of the diffusion barrier liner 20′. The first conductive metalplug 25 includes vertical sidewall portions (i.e., element 21′) thatextend upward from an uppermost surface of the first conductive metalplug 25. The interconnect structure further includes a second conductivemetal plug 30 located on an exposed surface of the first conductivemetal plug 25 and the exposed surface of each vertical sidewall portions21′. As shown in FIG. 9, left hand side, each of the diffusion barrierliner 20′, the vertical sidewall portions 21′, and the second conductivemetal plug 30 have an uppermost surface that is co-planar with anuppermost surface of the interconnect dielectric material 12.

While the present disclosure has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present disclosure. It is therefore intended that the presentdisclosure not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

What is claimed is:
 1. A method of forming a semiconductor structure,said method comprising: forming at least one opening within aninterconnect dielectric material; and forming an anti-fuse structurewithin the least one opening, wherein said forming the anti-fusestructure comprises: forming a contiguous layer of a diffusion barriermaterial on an exposed uppermost surface of the interconnect dielectricmaterial and at least within the at least one opening; forming acontiguous layer of a first conductive metal on an exposed surface ofthe contiguous layer of the diffusion barrier material; performing areflow anneal which causes portions of the contiguous layer of the firstconductive metal to flow into the at least one opening forming a firstconductive metal plug within the at least one opening, wherein aremaining portion of the contiguous layer of the first conductive metalwhich is present inside and outside the at least one opening remains incontact with said first conductive metal plug; forming a contiguouslayer of an anti-fuse material on exposed surfaces of the firstconductive metal plug and the remaining portion of the contiguous layerof the first conductive metal; forming a contiguous layer of a secondconductive metal on an exposed surface of the contiguous layer of theanti-fuse material; and removing a portion of the contiguous layer ofthe second conductive metal, a portion of the contiguous layer of theanti-fuse material, remaining portions of the contiguous layer of thefirst conductive metal, and a portion of the contiguous layer of thediffusion barrier material that are located outside of the at least oneopening.
 2. The method of claim 1, wherein said forming the at least oneopening within the interconnect dielectric material includes lithographyand etching.
 3. The method of claim 1, wherein said forming thecontiguous layer of the diffusion barrier material includes selecting amaterial that prevents diffusion of a conductive metal into theinterconnect dielectric material, and depositing said material.
 4. Themethod of claim 3, wherein said material that prevents diffusion of theconductive metal into the interconnect dielectric material includes Co,Ir, Pt, Pd, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W, or WN.
 5. Themethod of claim 1, wherein said first conductive metal of the contiguouslayer of the first conductive metal comprises a conductive metal, analloy comprising at least two conductive metals, a conductive metalsilicide or combinations thereof.
 6. The method of claim 5, wherein saidfirst conductive metal of said contiguous layer of the first conductivemetal is selected from the group consisting of Cu, W, Al and an alloythereof.
 7. The method of claim 1, wherein said reflow anneal isperformed at a temperature from 150° C. to 400° C.
 8. The method ofclaim 7, wherein said reflow anneal is performed in ahydrogen-containing ambient.
 9. The method of claim 7, wherein saidreflow anneal is performed in a nitrogen-containing ambient.
 10. Themethod of claim 7, wherein said first conductive metal plug and saidremaining portion of the contiguous layer of the first conductive metalare of unitary construction.
 11. The method of claim 1, wherein saidforming the contiguous layer of the anti-fuse material includesselecting an insulator material or a semiconductor material, anddepositing said insulator material or said semiconductor material. 12.The method of claim 11, wherein said contiguous layer of the anti-fusematerial comprises silicon dioxide, hafnium dioxide, nickel oxide,tantalum oxide, copper oxide, amorphous silicon carbide, amorphoussilicon, diamond like carbon or any combination thereof.
 13. The methodof claim 1, wherein said forming the contiguous layer of the secondconductive metal includes selecting a conductive metal that is the sameas that of the contiguous layer of the first conductive metal.
 14. Themethod of claim 1, wherein said forming the contiguous layer of thesecond conductive metal includes selecting a conductive metal that isdifferent from that of the contiguous layer of the first conductivemetal.
 15. The method of claim 1, wherein said removing the portion ofthe contiguous layer of second conductive metal, the portion of thecontiguous layer of the anti-fuse material, the remaining portions ofthe contiguous layer of the first conductive metal, and a portion of thecontiguous layer of the diffusion barrier material that are locatedoutside of the at least one opening comprises planarization, grinding ora combination thereof.
 16. The method of claim 1, further comprisingforming an interconnect structure located within a portion of theinterconnect dielectric material that lies laterally adjacent theinterconnect dielectric material including the anti-fuse structure, andat a same time as that of said forming the anti-fuse structure.
 17. Themethod of claim 16, wherein said forming the interconnect structurecomprises: forming the contiguous layer of the diffusion barriermaterial on an exposed uppermost surface of the interconnect dielectricmaterial and within at least one other opening located within aninterconnect area of the interconnect dielectric material; forming thecontiguous layer of the first conductive metal on an exposed surface ofthe contiguous layer of the diffusion barrier layer; performing thereflow anneal which causes portions of the contiguous layer of the firstconductive metal to flow into the at least one other opening forming thefirst conductive metal plug within the at least one other opening,wherein a remaining portion of the contiguous layer of the firstconductive metal which is present inside and outside the at least oneother opening remains in contact with said first conductive metal plug;forming a mask on said interconnect area, prior to forming thecontiguous layer of an anti-fuse material of the anti-fuse structure;removing the mask; forming the contiguous layer of the second conductivemetal on an exposed surface of the first conductive plug and remainingportions of the contiguous layer of the first conductive material in theinterconnect area; and removing the portion of the contiguous layer ofthe second conductive metal, remaining portions of the contiguous layerof the first conductive metal, and a portion of the contiguous layer ofthe diffusion barrier material that are located outside of the at leastone other opening.